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x86 & Arm Rival, RISC-V architecture delivers 10 billion cores

Calista Redmond, CEO of RISC-V International, announced at Embedded World that there are currently 10 billion RISC-V cores on the market.

The ARM RISC-V architecture has shipped 10 billion cores and is said to be more important than the x86 and ARM architecture in the future

RISC-V, pronounced “risk five,” is an open-standard instruction set architecture (ISA) provided under open-source licenses that are free to use. The base set of instructions contains naturally aligned fixed-length 32-bit instructions, and the ISA supports variable-length extensions, meaning that each instruction within 16-bit packets can be of any numeric length. The instruction set is available in 32-bit and 64-bit address space variants and was created for a wide range of applications. Different subsets support everything from tiny embedded systems to personal computers to supercomputers with vector processors and warehouse-scale parallel computers.

Calista Redmond said open standards are key.

Linux does it for software and we do it for hardware. We estimate that there are 10 billion RISC-V cores on the market.

But getting to 10 billion wasn’t a quick task. It is reported that it took 17 years of trial and error for the ARM architecture to reach the 2008 milestone. On the other hand, it took RISC-V only twelve years to reach ten billion. Redmond anticipates that the number of RISC-V processor cores will likely reach eighty billion by 2025.

Source: Embedded World 2022.

Included with this news was the announcement of approval for the new four specifications and extensions starting this year. The four new specifications are:

  • RISC-V specification for SBI architects a firmware layer between the hardware platform and the operating system kernel that uses a binary application interface in supervisor mode (S mode or VS mode). This abstraction enables common platform services across all RISC-V operating system implementations. Many RISC-V members have already implemented the RISC-V SBI specification in their RISC-V solutions, so ratification of the specification ensures a standard approach across the RISC-V ecosystem and compatibility. The development and ratification of this specification was led by Rivos’ Atish Patra, with work carried out by the Platform Horizontal Steering Committee.
  • RISC-V UEFI protocols bring existing UEFI standards to RISC-V platforms. Development and ratification of this specification was led by Sunil VL, Ventana Micro, and Philipp Tomsich, VRULL GmbH, with the work being performed in the Privileged Software Technical Working Group.
  • E-Trace for RISC-V defines a highly efficient processor tracing approach that uses branch tracing that is ideal for debugging any type of application, from tiny embedded designs to super powerful computers. The E-Trace for RISC-V documentation specifies the signals between the RISC-V core and the encoder (or input port), a compressed branch trace algorithm, and a packet format to encapsulate compressed branch trace information. Development and ratification of this specification was led by Gajinder Panesar of Picocom and RISC-V’s E-Trace Task Group.
  • RISC-V Zmmul Multiply Only enables low-cost implementations that require multiplication operations but not division and is part of the RISC-V Unprivileged Specification. Development and ratification of this extension was led by Allen Baum, with the work being conducted in the Unprivileged ISA Committee.

News Sources: IT Home, RISV.org